There are two approaches for simulating Memory as well as learning in artificial intelligence; the functionalistic approach and the cognitive approach. The necessary condition to put the second approach into account is to provide a model of brain activity that contains a quite good congruence with observational facts such as mistakes and forgotten experiences. Given that human Memory has a solid core that includes the components of our identity, our family and our hometown, the major and determinative events of our lives, and the countless repeated and accepted facts of our culture, the more we go to the peripheral spots the data becomes flimsier and more easily exposed to oblivion. It was essential to propose a model in which the topographical differences are quite distinguishable. In our proposed model, we have translated this topographical situation into quantities, which are attributed to the nodes. The result is an edge-weighted graph with mass-based values on the nodes which demonstrates the importance of each atomic proposition, as a truth, for an intelligent being. Furthermore, it dynamically develops and modifies, and in successive phases, it changes the mass of the nodes and weight of the edges depending on gathered inputs from the environment.

The demand of self-Testing proportionally increases with Memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-Testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-Testing. In the proposed Memory Test Algorithm, the self-Testing as well as self-repair mechanisms are incorporated. This scheme repairs the detected faults and is easily integrated with SoC design. Here, an attempt has been made to implement the Memory built-in-self-repair (MBISR) architecture to Test and repair the faults from the embedded memories. It is little, and it supports at-fast Test without timing penalty during its operation. The proposed method is a better alternative in speed and low area overhead. Thus, it plays a significant role in yield improvement.

Introduction: The aim of the present study was to examine the Memory types’ disorders in multiple sclerosis.Method: The research design is causal- comparative method in which two groups (females with multiple sclerosis and healthy females) are compared. For this purpose, 25 MS patients from MS Society of Tabriz and Tehran were selected by convenient sampling in autumn and winter 2014 as the case group, and 25 females with no history of chronic mental and neurological, psychiatric or psychological diseases or disorders, by matching with the case group, among the general population, and they completed the prospective/ retrospective Memory questionnaire (PRMQ). Collected data were analyzed by multivariate analysis of variance (MANOVA).Results: The results indicated that reported Memory errors in MS patients were more in comparing with healthy subjects.Conclusion: The findings have many practical implications for MS patients, their families, and especially the therapists of the patients.

The domain of Very Large Scale Integrated (VLSI) circuit Testing has experienced advancements in methodologies for fault detection, which are crucial for addressing the complexities of modern applications. Traditional Testing techniques frequently fall short in achieving precise fault localization, highlighting the necessity for the development of enhanced methodologies. This paper endeavors to investigate the implementation of an optimized Test generation Algorithm aimed at improving Testing efficiency and increasing fault coverage. In this study, we utilized a (PSO)-enhanced FAN (fan-out-oriented Algorithm) applied to ISCAS'89 benchmark circuits. The optimization process involved refining the decision trees utilized in the FAN Algorithm through a rigorously defined cost function, which strikes a balance between accuracy, complexity, and operational efficiency. The results indicate improvement in both fault coverage and detection efficiency. Furthermore, the optimization process resulted in a reduction of required Test vectors, thereby enhancing Testing efficiency, particularly in high-volume production environments. The study also introduces the development of diagnostic metrics that provide deeper insights into circuit failures and proposes design-for-Testability techniques to improve reliability. The integration of PSO within the FAN Algorithm not only facilitates the generation of robust Test solutions but also produces high-quality Test vectors.

Nowadays, it is common to find optimal point of the dynamic problem; dynamic problems whose optimal point changes over time require Algorithms which dynamically adapt the search space instability. In the most of them, the exploitation of some information from the past allows to quickly adapt after an environmental change (some optimal points change). This is the idea underlining the use of Memory in the field, which involves key design issues concerning the Memory content, the process of Memory update, and the process of Memory retrieval. With use of the Aging Best Solution and Keeping Diversity in Population, the speed convergence of Algorithm can be increased. This article presents a genetic Algorithm based on Memory for dealing with dynamic optimization problems and focuses on explicit placement of Memory schemes, and performs a comprehensive analysis on current design of Moving Peaks Benchmark (MPB) problem. The MPB problem is the most proper benchmark for simulation of dynamic environments. The experimental study show the efficiency of the proposed approach for solving dynamic optimization problems in comparison with other Algorithms presented in the literature.

Background and Aim: Today, Bilingualism is a developing phenomenon which half of the world population is bilingual. Auditory system is the main route to language learning, so it is expected that bilingualism has an effect on functions of the auditory system. Auditory Memory is one of the auditory processes which is a cornerstone of linguistic skills and learning process growth, so that, it has an important role in language learning. In this paper, functions of the auditory Memory in monolinguals and precocious bilinguals have been investigated through dichotic auditory-verbal Memory Test.Methods: A cross sectional-contrastive study of the Persian version of dichotic auditory-verbal Memory Test has been carried out among 30 monolingual and 30 bilingual persons. The participants were chosen from both sexes in the age range of 18-30, and Test scores have been compared in both groups and sexes.Results: Mean score of dichotic auditory-verbal Memory Test in monolinguals was 5.47 (from 10), with a standard deviant of 0.55, and in bilinguals were 7.52, with a standard deviant of 0.90, which statistically, it showed a significant difference in scores between the two groups (p<0.001). There was no significant difference among men and women’s scores in monolingual (p=0.06) and bilingual (p=0.10) groups.Conclusion: Results of this limited research showed that there was a considerable functional difference between monolinguals and bilinguals in dichotic auditory-verbal Memory Test.Therefore, it seems precocious bilingualism has a positive effect on the auditory Memory.